[Mep-dev] PRNG seems to work

[Michelle]

In the absence of thoroughly testing it, I can't state definitively that it is a wholly successful implementation, but the MEP "yet another pseudorandom number generator" VHDL module appears to work. Source code included below.
 
-Michelle W5NYV 
 
 
----------------------------------------------------------------------------------
-- Company: Optimized Tomfoolery
-- Engineer: Michelle Thompson
-- 
-- Create Date:    16:34:20 05/28/2010 
-- Design Name: BERT
-- Module Name:    PRNG - Behavioral 
-- Project Name: MEP
-- Target Devices: 
-- Tool versions: 
-- Description: Pseudorandom Number Generator for Bit Error Rate Tester
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity PRNG is
    Port ( prn_out : out  BIT_VECTOR (7 downto 0);
           initial_value : in  BIT_VECTOR (7 downto 0));

 --declare signals here
 --clock
  signal Tic_Toc : STD_LOGIC := '0';
 --set signals
  signal Set0 : STD_LOGIC := '0';
  signal Set1 : STD_LOGIC := '0';
  signal Set2 : STD_LOGIC := '0';
  signal Set3 : STD_LOGIC := '0';
  signal Set4 : STD_LOGIC := '0';
  signal Set5 : STD_LOGIC := '0';
  signal Set6 : STD_LOGIC := '0';
  signal Set7 : STD_LOGIC := '1';  
 --reset signals
  signal Reset0 : STD_LOGIC := '0';
  signal Reset1 : STD_LOGIC := '0';
  signal Reset2 : STD_LOGIC := '0';
  signal Reset3 : STD_LOGIC := '0';
  signal Reset4 : STD_LOGIC := '0';
  signal Reset5 : STD_LOGIC := '0';
  signal Reset6 : STD_LOGIC := '0';
  signal Reset7 : STD_LOGIC := '0';  
 --results signals
  signal R7 : BIT := '0';
  signal R6 : BIT := '0';
  signal R5 : BIT := '0';
  signal R4 : BIT := '0';
  signal R3 : BIT := '0';
  signal R2 : BIT := '0';
  signal R1 : BIT := '0';
  signal R0 : BIT := '0';
 --feedback signals
  signal F3 : BIT := '0';
  signal F2 : BIT := '0';
  signal F1 : BIT := '0';
  signal F0 : BIT := '0';
     
end PRNG;
 
architecture Behavioral of PRNG is
--clock source
 component clock
  generic (PULSE_WIDTH : TIME);
  port (clock: out STD_LOGIC);
 end component;
 
 
--d flip flop component
 component d_flip_flop
  port (data_in: in BIT;
    clock: in STD_LOGIC;
    data_out: out BIT;
    set: in STD_LOGIC;
    reset: in STD_LOGIC);
 end component;

--xor gate component
 component exor
  port ( xor_data_in_a : in  BIT;
     xor_data_in_b : in  BIT;
     xor_data_out  : out  BIT);
 end component;

begin
 Set7 <= '0' after 10 ns;

 Synch: clock
  generic map (PULSE_WIDTH => 5 ns)
  port map (Tic_Toc);
  
 Do_xor_01: exor
  port map (F0, R2, F1);
  
 Do_xor_02: exor
  port map (F1, R3, F2);
  
 Do_xor_03: exor
  port map (F2, R7, F3);
 
 Drive_Flip_Flop_0: d_flip_flop
  port map (R1, Tic_Toc, R0, Set0, Reset0);
  
 Drive_Flip_Flop_1: d_flip_flop
  port map (R2, Tic_Toc, R1, Set1, Reset1);
  
 Drive_Flip_Flop_2: d_flip_flop
  port map (R3, Tic_Toc, R2, Set2, Reset2);
 Drive_Flip_Flop_3: d_flip_flop
  port map (R4, Tic_Toc, R3, Set3, Reset3);
 Drive_Flip_Flop_4: d_flip_flop
  port map (R5, Tic_Toc, R4, Set4, Reset4);
 Drive_Flip_Flop_5: d_flip_flop
  port map (R6, Tic_Toc, R5, Set5, Reset5);
 Drive_Flip_Flop_6: d_flip_flop
  port map (R7, Tic_Toc, R6, Set6, Reset6);
 Drive_Flip_Flop_7: d_flip_flop
  port map (F3, Tic_Toc, R7, Set7, Reset7);
end Behavioral;