[Mep-dev] VHDL bit error rate tester update

[Michelle]

A VHDL module was written today that implements a pseudrandom number generator (PRNG) with an external clock. This is another small step towards a bit error rate tester (BERT). KB5MU talked today about what a BERT looks like, and I learned that they come in pairs - there is a transmit side part of the tester, and a more complex receive side of the tester. It all made sense, and I will post a drawing of where we're going with the VHDL later tonight. 

I made a quick summary of the website statistics for May, and am reading the documentation at Open Cores to see how to start a project. 
 -Michelle W5NYV