[Mep-dev] FPGA 1.1 drawing and questions

[Bob McGwier]

On 3/30/2010 4:12 PM, Michelle wrote:
> Here's today's sketch of the FPGA. It now has stuff coming out the other side!
>
> One of the comments was to go ahead and connect the FGPA to a processor, like the TI OMAP in the Beagleboard, directly. I'm assuming that it's connected directly in a large parallel interface to memory. There's a lot of available pins on the TI OMAP.
>
> Another FPGA output could be IPv6 and IPv4 packets.
> -Michelle W5NYV
>
>
>
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In the FPGA prior to the costa's loop you will need a nonlinear 
equalizer and DC elimination.   The QSD, done in this case with some 
fairly high speed switches and baseband filtering most likely,  will 
have both amplitude and phase imbalance in the I/Q legs and further,  it 
is frequency (rate of switching the sampling "capacitors") dependent.

I have devised an algorithm which really makes the difference in the 
performance of these devices (out of necessity).  Especially for digital 
signals, this is imperative.

Suppose Z is the incoming signal AFTER the QSD.  Z* (complex conjugate) 
is taken, and a filter is applied to Z*, and the applied to a delayed 
copy of Z.  This sufficiently eliminates the image rejection imbalance 
to make it an unimportant part of the communications system.

An ASSUMPTION of the algorithm is that there is NO DC component, so it 
must be eliminated before  F(Z*)(n) is applied to Z(-n) and the 
reestimation of F is done.

Bob

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